US4815130A - Stream cipher system with feedback - Google Patents
Stream cipher system with feedback Download PDFInfo
- Publication number
- US4815130A US4815130A US07/097,307 US9730787A US4815130A US 4815130 A US4815130 A US 4815130A US 9730787 A US9730787 A US 9730787A US 4815130 A US4815130 A US 4815130A
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- shift register
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
Definitions
- the invention relates generally to a cipher system, and it relates, in particular, to a stream cipher system employing feedback and a logic function.
- Cipher systems are used to encode data for transmission in such a way that an unintended recipient of the transmission cannot decipher nor understand the message contained in the transmission without an understanding of the details of the enciphering system and possibly also a key employed in the enciphering. In this way proprietary or highly sensitive data can be transmitted over common airways. These transmissions are themselves understood to involve unsecure data paths which can be easily intercepted by unintended recipients. However, if these recipients cannot perform the required deciphering to reproduce the original data, the security of the system can be maintained.
- Cipher systems are generally divided into two classes, block ciphers and stream ciphers.
- a block cipher operates upon a multi-bit block to transform the bit sequence within the block into another sequence having possibly a different block size. However, the blocks remain independent of each other.
- a stream cipher individually changes each bit in a generally infinite stream. In the general case of a stream cipher, the transformation of a particular bit may depend upon the values of neighboring bits but there is no defined block.
- One type of stream cipher is the auto-key cipher shown schematically in FIGS. 1A and 1B.
- FIG. 1A illustrates the basic operation of the encipherer.
- a digital message arrives in plain text, that is, in uneciphered form, on an input line 12 which is connected to the serial input of a shift register 14.
- the shift register 14 shifts to the left, as illustrated, in synchronism with the bit rate of the input line 12. If the shift register 14 is m bits long, then after m periods of the message, the input appears on the output 16 of the shift register. This delayed bit is then added bit by bit in an adder 18 to the current bit of the message to produce a cipher text on the output 20 of the encipherer.
- the design of the decipherer as illustrated in FIG. 1B, closely resembles that of the encipherer.
- the cipher text is received on an input line 22 and is added in an adder 24 to the output 26 of an m-bit shift register 28 to produce the deciphered text or message on an output line 30.
- a binary adder 24 acts as well as a subtractor.
- the deciphered text is also led into the input of the shift register 28 where it reappears m bits later on the output 26.
- the cipher test differs significantly from the plain text message and the details of the enciphering must be known if the enciphered text is to be deciphered. Nonetheless, the cipher system illustrated in FIGS. 1A and 1B is relatively simple and a determined recipient can break the code, particularly if the general concept of the cipher system is known.
- the most commonly used stream cipher employs a key generator. As shown in FIG. 2A for an encipherer and in FIG. 2B for a decipherer, both consist of an identical key generator 32.
- a message arrives on an input line 34 and is added to the output of the key generator 32 in an adder 36 which in modulo 2 arithmetic is an exclusive OR gate.
- the output 38 of the adder 36 contains the cipher text.
- the cipher text arriving on the input line 40 is differenced with the output of a key generator 32 in a subtractor 41.
- modulo 2 arithmetic subtraction and addition are the same so that the sum of the two signals produces on the output 42 the original message.
- the key generator 32 present in both the encipherer and decipherer produces a sequence of bits independently of the contents of the message for the cipher text.
- the key generator 32 in each of the encipherer and decipherer must be producing the same sequence and be synchronized identically with the message. Security is maintained by maintaining the output of the key generator 32 in confidence. Its output is never transmitted in the clear.
- Key generator ciphers have the advantage that if one bit of the cipher text is inverted because of a noisy path, the error is confined to a single bit of the deciphered message and does not propagate to other bits. However, the security provided by many key generator ciphers is considered insufficient.
- FIG. 3 A special case of a key generator cipherer is illustrated in FIG. 3. This system was proposed to operate with the National Bureau of Standards (NBS) Data Encryption Standard (DES).
- NBS National Bureau of Standards
- DES Data Encryption Standard
- the DES system relies upon a 56-bit key 44.
- Both an input register 46 and an output register 48 are 64 bits wide.
- a DES circuit 50 takes the outputs of the key 44 and the input register 46, operating as a stream to block deserializer, and performs an algorithm on the block according to the Data Encryption Standard and outputs a 64 bit block to the output register 48.
- the output register 48 is also a shift register and its contents are shifted out as both a serial input 52 to the input register 46 and to an adder 54.
- the input 56 to the system is the other addend to the adder 54 which produces a signal on the output line 58.
- This structure is identical for both an encipherer and a decipherer for binary symbols.
- the input line 56 carries the message while the output line 58 carries the cipher text.
- the cipher text is on the input line 56 while the output line 58 carries the clear text message.
- FIGS. 4A and 4B Similar circuitry has been applied to cipher-blocking chaining, as illustrated in FIGS. 4A and 4B for an encipherer and a decipherer respectively.
- the circuitry is similar to that in FIG. 3 except that in the encipherer, the input 60 to the input register 46 is connected to the output line 62 of the adder 54 so that the cipher text is inputted into the key generator.
- the input line 64 to the input register 46 is connected to the input line 66 of the adder 54 so that the cipher text is inputted here as well.
- feedback is employed which is a function of the output of the DES circuit 50.
- the invention can be summarized as a method of enciphering in which the message is added bit by bit to the output of a shift register and the sum forms the serial input to the same shift register.
- the parallel outputs of the shift register are transformed with a logic function to a single output which is then added to the message to form the cipher text.
- FIGS. 1A and 1B are schematic diagrams of auto-key ciphers of the prior art.
- FIGS. 2A and 2B are schematic diagrams of stream ciphers of the prior art.
- FIG. 3 is a schematic diagram of a key generator cipher of the prior art.
- FIGS. 4A and 4B are schematic diagrams of blocked chaining ciphers of the prior art.
- FIGS. 5A and 5B are schematic diagrams of an encipherer and a decipherer, respectively, of a first embodiment of the present invention.
- FIGS. 6A and 6B are schematic diagrams of an encipherer and a decipherer, respectively, of a second embodiment of the present invention.
- FIGS. 7A and 7B are schematic diagrams of an encipherer and a decipherer, respectively, of a third embodiment of the present invention.
- FIGS. 8, 9, 10, 11 and 12 are schematic diagrams of embodiments of logic functions usuable with the present invention.
- FIG. 5A For an encipherer and FIG. 5B for a decipherer.
- the plain text message is led in on an input line 64 to a first adder 66.
- the output 68 of the last bit of an l-bit shift register 70 is also led into the adder 66 and the sum is connected to the serial input 72 of the shift register 70.
- the l parallel outputs of the shift register 70 are all led to a logic function 74 which produces a single output 76.
- This single output 76 is then added to the current bit of the message on the input line l64 in a second adder 78 which produces on its output line 80 the desired cipher text.
- the decipherer is arranged in a similar fashion but the cipher text on the input line 82 is subtracted from the output of the logic function 74 in a subtractor 84 to produce the deciphered message on its output line 86.
- the deciphered message is subtracted in a subtracter 88 from the output 90 of the last bit of the l-bit shift register 70.
- the l parallel outputs of the shift register 70 are led into the logic function 74.
- the subtractors 84 and 88 can be adders in binary systems.
- log 2 n binary bits are required to represent the complete symbol set.
- the shift register 70 may be considered as log 2 n binary shift registers, each having l/log 2 n bits.
- the adders 66 and 78 perform modulo-n addition while the adders 84 and 88 in the decipherer perform modulo-n subtraction.
- the cipher system of this invention incorporates features of both the auto-key cipher of FIGS. 1A and 1b and the feedback ciphers of FIGS. 3, 4A and 4B. It operates with a key initially inserted into the shift registers 70 in both the encipherer and decipherer without the need for a special key register 44.
- the invention provides higher security than the available with the auto-key cipher but without the hardware complexity associated with the DES ciphers of FIGS. 3, 4A and 4B.
- a possible disadvantage of the cipher system of the invention is that if a single bit of the cipher text is inverted in transmission then, because of the feedback loop, the remaining or following text cannot be correctly deciphered. the error is not confined to a segment of the message. However, in some systems, such a propagating error is not a major problem.
- One such system incorporates error detection coding in the message. When an error is detected on the receiving side, the transmitting side is requested to retransmit the entire message regardless of whether one or multiple errors have been detected.
- a further embodiment of the invention is shown for an encipherer in FIG. 6A and a decipherer n FIG. 6B.
- the shift register 70 of the encipherer of the previously described embodiment is divided into two shift registers 92 and 94.
- the output 72 of the adder 66 is led into the shift register 92 having l - m bits.
- the l - m parallel outputs of this shift register 92 are connected to a logic function 96 of similar but smaller construction to the logic function 74 and it has its one output 98 connected to the adder 78.
- the output 100 of the oldest bit in the shift register 92 is connected to the serial input of the shift register 94 having m bits.
- the output of this shift register 94 is connected to the adder 66, completing the feedback loop.
- the output line 86 of the subtractor 84 is led into a subtractor 102 which also receives the output of the oldest bit of a shift register 104 having l - m bits.
- the output of the subtractor 102 is led into the serial input of an m-bit shift register 106, the output 108 of which is connected to the serial input of the shift register 104.
- the l - m parallel outputs of the shift register 104 are connected to the logic function 96 the output of which is connected to the subtractor 84.
- the logic function 96 associated with this embodiment is less complex because it does not process the m bits of the shift registers 94 and 104.
- the security strength of this embodiment of the cipher system is of course weaker than that of the previously described embodiment.
- FIG. 7A A third binary embodiment of the cipher system of the present invention is shown in FIG. 7A for the encipherer and in FIG. 7B for the decipherer.
- the structure of the encipherer very closely resembles the structure of the encipherer of the first embodiment shown in FIG. 7A except that an additional adder 110 is inserted into the output line 80 to add the output of the adder 78 and the newest bit in the shift register 70 of the encipherer.
- the output of the adder 112 carries the ciphered text for transmission.
- the additional adder 110 is intended to guarantee that a change of a single bit in the message 64 will have a high probability of changing the ciphered text on the output line 112.
- the inclusion of the additional adder 112 requires that another adder 114 be included in the feedback loop of the encipherer that adds the newest bit in the shift register 70 to the feedback loop. Also required by this change is the inclusion of an adder 116 to the message output 86 of the decipherer at a point beyond its feedback to the adder/subtractor 88. The adder 116 also adds the newest bit in the shift register 70 to the output of the adder 84 to produce a plain text message on its output 118.
- the described embodiments have used adders in the encipher and subtractors in the decipherer.
- the invention includes cipher systems in which a subtractor in the encipherer is balanced by a corresponding adder in the decipher and vice versa.
- an adder can add or subtract while a subtractor performs the opposite operation.
- the logic functions 74 and 96 can be implemented in several ways.
- a logic function can always be implemented by a read-only memory (ROM) having a log 2 n-bit output for a symbol size of n.
- ROM read-only memory
- a ROM is advantageous in that its contents can be designed not only so that there are not only equal numbers of output symbols distributed among the address locations, but also so that their distribution is such that it is virtually impossible to derive its contents by investigating only a sequence of its outputs.
- the method of establishing a nearly optimal relationship between the inputs to the logic function and its output within a chosen logic function structure relies on standard statistical techniques.
- the disadvantage of using a single ROM as the logic function is that its size increases exponentially with the number of input lines so that the implementation becomes too complicated for larger values of l.
- the second embodiment of the cipher system illustrated in FIGS. 6A and 6B reduces the complexity of the ROM but only at the expense of weaker security.
- FIG. 8 A generalized method for reducing the size of individual logic functions is illustrated in FIG. 8 for a two-stage transformation logic.
- the k 1 outputs of the logic functions 120, 122 and 124 of the first stage are led into the k 1 inputs of a second stage logic function 126 that produces the one desired output 128.
- the logic functions 120-126 can be either ROMs or other types of gate circuits. Examples of multi-stage logic functions are shown in FIGS. 9, 10 and 11. It should be noted that the logic circuit of FIG. 9 is the sum of one direct input 130 and the output of various multiple input gates.
- FIG. 12 A more realistic logic function implemented with gates is shown in FIG. 12 in which 36 input lines are combined in various AND gates and OR gates to form a single output.
- the designations on the pin inputs refer to the bit numbers on the shift register 70.
- the connection of the first stage inputs to the output of the shifter register in the various embodiments of the cipher system should be chosen so that the output of the overall transformation appears random.
- Some general guidelines are that contiguous outputs of the shift register should be connected to different sections of the input stage of the logic function.
- the connections between the shift register and the logic function should appear random and neighboring inputs to the logic function should not be connected to equally spaced outputs of the shift register.
- the present invention is superior to known prior cipher systems in that it provides strong security and creates more confusion for cryptanalysis while using fairly simple circuitry.
- the more secure embodiments of the invention use a large number of inputs to the logic function and rely less upon a multi-stage logic function.
Abstract
Description
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US07/097,307 US4815130A (en) | 1986-10-03 | 1987-09-14 | Stream cipher system with feedback |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US91457286A | 1986-10-03 | 1986-10-03 | |
US07/097,307 US4815130A (en) | 1986-10-03 | 1987-09-14 | Stream cipher system with feedback |
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US91457286A Continuation | 1986-10-03 | 1986-10-03 |
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US4815130A true US4815130A (en) | 1989-03-21 |
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US07/097,307 Expired - Lifetime US4815130A (en) | 1986-10-03 | 1987-09-14 | Stream cipher system with feedback |
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Cited By (40)
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US4876718A (en) * | 1987-03-12 | 1989-10-24 | Zenith Electronics Corporation | Secure data packet transmission system and method |
US5014313A (en) * | 1989-07-07 | 1991-05-07 | Motorola, Inc. | Text modifier |
US5086468A (en) * | 1989-07-07 | 1992-02-04 | Motorola, Inc. | Text modifier |
US5159634A (en) * | 1991-09-13 | 1992-10-27 | At&T Bell Laboratories | Cryptosystem for cellular telephony |
US5195136A (en) * | 1991-09-30 | 1993-03-16 | Motorola, Inc. | Method and apparatus for data encryption or decryption |
US5231667A (en) * | 1990-12-10 | 1993-07-27 | Sony Corporation | Scrambling/descrambling circuit |
US5323463A (en) * | 1991-12-13 | 1994-06-21 | 3Com Corporation | Method and apparatus for controlling the spectral content of a data stream |
EP0666663A1 (en) * | 1994-02-04 | 1995-08-09 | Koninklijke KPN N.V. | Cryptographic device |
US5444781A (en) * | 1993-08-23 | 1995-08-22 | Apple Computer Inc. | Method and apparatus for decryption using cache storage |
US5809147A (en) * | 1994-03-18 | 1998-09-15 | Koninklijke Ptt Nederland | Device for cryptographically processing data packets and method of generating cryptographic processing data |
US5859912A (en) * | 1996-03-22 | 1999-01-12 | General Electric Company | Digital information privacy system |
US5978481A (en) * | 1994-08-16 | 1999-11-02 | Intel Corporation | Modem compatible method and apparatus for encrypting data that is transparent to software applications |
US6122379A (en) * | 1996-05-30 | 2000-09-19 | Deloitte & Touche Inc. | Method and apparatus for performing simultaneous data compression and encryption |
US6215876B1 (en) | 1997-12-31 | 2001-04-10 | Transcrypt International, Inc. | Apparatus for and method of detecting initialization vector errors and maintaining cryptographic synchronization without substantial increase in overhead |
US6249582B1 (en) | 1997-12-31 | 2001-06-19 | Transcrypt International, Inc. | Apparatus for and method of overhead reduction in a block cipher |
US6360320B2 (en) * | 1997-04-23 | 2002-03-19 | Sony Corporation | Information processing apparatus, information processing method, information processing system and recording medium using an apparatus id and provided license key for authentication of each information to be processed |
US6393125B1 (en) * | 1997-07-11 | 2002-05-21 | Zarlink Semiconductor Inc. | Initializer for a confusion data generator |
US6460137B1 (en) * | 1995-06-02 | 2002-10-01 | Fujitsu Limited | Encryption processing system |
US6731754B1 (en) | 1996-06-21 | 2004-05-04 | Netcomsec Co., Ltd. | Apparatus and method for maintaining and transmitting secret contents of a signal |
US20050053240A1 (en) * | 2003-09-09 | 2005-03-10 | Peter Lablans | Ternary and higher multi-value digital scramblers/descramblers |
US6891952B1 (en) * | 1998-12-07 | 2005-05-10 | International Business Machines Corporation | Dynamic key generation and confidential synchronization of encryption components |
US20050184888A1 (en) * | 2004-02-25 | 2005-08-25 | Peter Lablans | Generation and detection of non-binary digital sequences |
US20050185796A1 (en) * | 2004-02-25 | 2005-08-25 | Peter Lablans | Ternary and multi-value digital signal scramblers, descramblers and sequence generators |
US20050194993A1 (en) * | 2004-02-25 | 2005-09-08 | Peter Lablans | Single and composite binary and multi-valued logic functions from gates and inverters |
US20060021003A1 (en) * | 2004-06-23 | 2006-01-26 | Janus Software, Inc | Biometric authentication system |
US20060031278A1 (en) * | 2004-08-07 | 2006-02-09 | Peter Lablans | Multi-value digital calculating circuits, including multipliers |
US20060227967A1 (en) * | 2005-04-11 | 2006-10-12 | Tomoki Nishikawa | Data processing system and method |
US7190787B1 (en) * | 1999-11-30 | 2007-03-13 | Intel Corporation | Stream cipher having a combiner function with storage based shuffle unit |
US20070110229A1 (en) * | 2004-02-25 | 2007-05-17 | Ternarylogic, Llc | Ternary and Multi-Value Digital Signal Scramblers, Descramblers and Sequence of Generators |
US20090128190A1 (en) * | 2004-02-25 | 2009-05-21 | Peter Lablans | Implementing Logic Functions with Non-Magnitude Based Physical Phenomena |
US7548092B2 (en) | 2004-02-25 | 2009-06-16 | Ternarylogic Llc | Implementing logic functions with non-magnitude based physical phenomena |
US20100164548A1 (en) * | 2004-09-08 | 2010-07-01 | Ternarylogic Llc | Implementing Logic Functions With Non-Magnitude Based Physical Phenomena |
WO2011001030A1 (en) * | 2009-06-29 | 2011-01-06 | Envault Corporation Oy | Method and arrangement for protecting file-based information |
US20110064214A1 (en) * | 2003-09-09 | 2011-03-17 | Ternarylogic Llc | Methods and Apparatus in Alternate Finite Field Based Coders and Decoders |
US8374289B2 (en) | 2004-02-25 | 2013-02-12 | Ternarylogic Llc | Generation and detection of non-binary digital sequences |
US8577026B2 (en) | 2010-12-29 | 2013-11-05 | Ternarylogic Llc | Methods and apparatus in alternate finite field based coders and decoders |
US8861725B2 (en) | 2012-07-10 | 2014-10-14 | Infineon Technologies Ag | Random bit stream generator with enhanced backward secrecy |
US8879733B2 (en) | 2012-07-10 | 2014-11-04 | Infineon Technologies Ag | Random bit stream generator with guaranteed minimum period |
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US5231667A (en) * | 1990-12-10 | 1993-07-27 | Sony Corporation | Scrambling/descrambling circuit |
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US5323463A (en) * | 1991-12-13 | 1994-06-21 | 3Com Corporation | Method and apparatus for controlling the spectral content of a data stream |
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EP0666663A1 (en) * | 1994-02-04 | 1995-08-09 | Koninklijke KPN N.V. | Cryptographic device |
US5809147A (en) * | 1994-03-18 | 1998-09-15 | Koninklijke Ptt Nederland | Device for cryptographically processing data packets and method of generating cryptographic processing data |
US5978481A (en) * | 1994-08-16 | 1999-11-02 | Intel Corporation | Modem compatible method and apparatus for encrypting data that is transparent to software applications |
US6460137B1 (en) * | 1995-06-02 | 2002-10-01 | Fujitsu Limited | Encryption processing system |
US5859912A (en) * | 1996-03-22 | 1999-01-12 | General Electric Company | Digital information privacy system |
US6122379A (en) * | 1996-05-30 | 2000-09-19 | Deloitte & Touche Inc. | Method and apparatus for performing simultaneous data compression and encryption |
US6731754B1 (en) | 1996-06-21 | 2004-05-04 | Netcomsec Co., Ltd. | Apparatus and method for maintaining and transmitting secret contents of a signal |
US6360320B2 (en) * | 1997-04-23 | 2002-03-19 | Sony Corporation | Information processing apparatus, information processing method, information processing system and recording medium using an apparatus id and provided license key for authentication of each information to be processed |
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